Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

Floating-Point Single-Precision Fused Multiplier-adder Unit on FPGA

The fused multiply-add operation improves many calculations and therefore is already available in some generalpurpose processors, like the Itanium. The optimization of units dedicated to execute the multiply-add operation is therefore crucial to achieve optimal performance when running the overlying applications. In this paper, we present a single-precision floating-point fused multiply-add opt...

Opensource Floating Point Adder

This is an open source floating point adder designed by Justin Schauer as a summer research project at Harvey Mudd College for Dr. David Harris. It was designed to fully conform to the IEEE 754 standard. In its fully-featured format, this adder supports all rounding modes: round to nearest even, round to plus infinity, round to minus infinity, and round to zero; it supports denormalized numbers...

A Single Precision Asynchronous Floating Point Multiplier

This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion o...

5. Implementation Results 32 Bits Ieee Parallel Floating Point Adder

A Novel Design of Reversible Floating Point Adder Architecture

This project revolves around the design and implementation of floating point adder architecture using reversible logic to improve the design in terms of the number of garbage outputs and the number of gates used. In recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it...